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Dual-Phase, Quick-PWM Controller
for IMVP6+ CPU Core Power Supplies
Shutdown
When SHDN goes low, the MAX17410 enters low-power
shutdown mode. PWRGD is pulled low immediately,
and the output voltage ramps down at 1/8th the slew
rate set by R TIME :
Phase Fault (PHASEGD)
The MAX17410 includes a phase fault output that sig-
nals the system that one of the two phases either has a
fault condition or is not matched with the other.
Detection is done by identifying the need for a large on-
t TRAN ( SHDN ) =
8 V OUT
( dV TARGET / dt )
time difference between phases to achieve or move
towards current balance. PHASEGD is forced low when
V CCI is below (0.6 x V FB ) or above (1.4 x V FB ).
where dV TARGET /dt = 12.5mV/μs x 71.5k Ω /R TIME is the
slew rate. Slowly discharging the output capacitors by
slewing the output over a long period of time keeps the
average negative inductor current low (damped
response), thereby eliminating the negative output-volt-
age excursion that occurs when the controller dis-
charges the output quickly by permanently turning on
the low-side MOSFET (underdamped response). This
eliminates the need for the Schottky diode normally con-
nected between the output and ground to clamp the
negative output-voltage excursion. After the controller
reaches the zero target, the MAX17410 shuts down
completely—the drivers are disabled (DL1 and DL2 dri-
ven high), the reference turns off, and the supply current
drops below 1μA.
When a fault condition—output UVLO or thermal shut-
down—activates the shutdown sequence, the protection
circuitry sets the fault latch to prevent the controller from
restarting. To clear the fault latch and reactivate the con-
troller, toggle SHDN or cycle V CC power below 0.5V.
Power Monitor (PMON)
The MAX17410 include a single-quadrant multiplier
used to determine the actual output power based on
the inductor current (the differential CS input) and out-
put voltage (CSN to GNDS). The buffered output of this
multiplier is connected to PWR and provides a voltage
relative to the output power dissipation:
V(PMON) = Kpwr x V(OUTS, GNDS) x V(CSPAVG,
CSN) / V(TIME, ILIM)
where V CSP - V CSN = I LOAD x R SENSE , and the power
monitor scale factor (Kpwr) is typically 21.25. If ILIM is
externally connected to a 5V rail to enable the internal
default/preset current-limit threshold, then the V(TIME,
ILIM) value to be used in the above equation is 225mV.
Do not use the power monitor in any configuration that
would cause its output V(PMON) to exceed (V CC - 0.5V).
PMON is pulled to ground when the MAX17410 is in
shutdown.
The power monitor allows the system to accurately
monitor the CPU’s power dissipation and quickly pre-
dict if the system is about to overheat before the signifi-
cantly slower temperature sensor signals an
overtemperature alert.
PHASEGD is high impedance when the controller oper-
ates in one-phase mode (DPRSLPVR high, or PSI low and
DPRSLPVR low). On exit to two-phase mode, PHASEGD
is forced high impedance for 32 switching cycles on DH2.
PHASEGD is low in shutdown. PHASEGD is forced high
impedance whenever the slew-rate controller is active
(output voltage transitions).
Temperature Comparator ( VRHOT )
VRHOT is an open-drain output of the internal compara-
tor. VRHOT is pulled low when the voltage at NTC goes
below the voltage at THRM. VRHOT is high impedance
in shutdown.
Fault Protection (Latched)
Output Overvoltage Protection
The overvoltage protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET
by drawing high current and blowing the battery fuse.
The MAX17410 continuously monitors the output for an
overvoltage fault. The controller detects an OVP fault if
the output voltage exceeds the set VID DAC voltage by
more than 300mV, regardless of the operating state.
During pulse-skipping operation (DPRSLPVR = high),
the OVP threshold tracks the VID DAC voltage.
When the OVP circuit detects an overvoltage fault while
in multiphase mode (DPRSLPVR = low, PSI = high), the
MAX17410 immediately forces DL1 and DL2 high, pulls
DH1 and DH2 low. This action turns on the synchro-
nous-rectifier MOSFETs with 100% duty and, in turn,
rapidly discharges the output filter capacitor and forces
the output low. If the condition that caused the overvolt-
age (such as a shorted high-side MOSFET) persists,
the battery fuse will blow. Toggle SHDN or cycle the
V CC power supply below 0.5V to clear the fault latch
and reactivate the controller.
When an overvoltage fault occurs while in one-phase
operation (DPRSLPVR = high, or PSI = low), the
MAX17410 immediately forces DL1 high, pulls DH1 low.
DL2 and DH2 remain low as phase two was disabled.
DL2 is forced high only when the output falls below the
UV threshold.
Overvoltage protection can be disabled through the no-
fault test mode (see the No-Fault Test Mode section).
______________________________________________________________________________________
37
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